The present invention relates generally to the data processing field, and more particularly, relates to a programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface.
DDR SDRAM use a source synchronous interface for reading and writing data. The source synchronous clock strobe on DDR SDRAM is named DQS. When data is read from a DDR SDRAM, the DQS clock strobe is driven by the SDRAM. The SDRAM edge aligns the DQS clock strobe with the data. It is the responsibility of the device receiving SDRAM read data to delay the incoming DQS and center the incoming DQS in the middle of the incoming data. Strobe centering relative to data is required to handle skew uncertainty between the DQS and data coming out of the SDRAM, as determined by the SDRAM specification. It is also required to handle skew uncertainty created by card wiring, card loading, and inter-signal interference (ISIS). Lastly, DQS centering is required to support the data latch setup and hold times.
When DDR interfaces are operated at high frequencies, tight tolerance is required for the circuitry used to implement the delay of DQS. A common method to account for process variation effects on DQS delay between different manufactured chips is to calibrate DQS delay at system startup time. Temperature and voltage also affect delay. Temperature and voltage can dynamically change during system operation. A common method to compensate for temperature and voltage fluctuations is to continually calibrate the DQS delay.
A need exists for an improved mechanism to implement the delay of DQS. It is desirable to provide such an improved mechanism to implement the delay of DQS that effectively compensates for temperature and voltage fluctuations during system operation.
A principal object of the present invention is to provide a programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface. Other important objects of the present invention are to provide such programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface substantially without negative effect and that overcomes many of the disadvantages of prior art arrangements.
In brief, a programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface is provided. A programmable compensated delay apparatus includes a reference delay calibration circuit for providing a measured number of delay elements in one cycle. A programmable delay register provides a desired delay value. A conversion logic is coupled to the reference delay calibration circuit and the programmable delay register for receiving both the measured number of delay elements in one cycle and the desired delay value. The conversion logic provides a number of required delay elements. A delay circuit is coupled to the conversion logic for receiving the number of required delay elements and providing the desired delay.
In accordance with features of the invention, a SDRAM control logic provides a refresh start signal to the reference delay calibration circuit for updating the delay circuit during each DDRAM refresh. The DQS clock strobe on the DDR SDRAM is applied to the delay circuit and delayed by the desired delay.